Computer Science 270

Computer Organization




The MIPS ADD Instruction: ADD $1, $2, $3
by Chris Parrish

The accompanying figure illustrates the data flow and control signals for the instruction ADD $1, $2, $3 on a singlecycle MIPS processor, assuming that register $2 holds 20 (base ten) and register $3 holds 30 (base 10).


COD 5.5: addi $t1, $t2, 100
by Mitch Perry

Well, what really happens is ... blah .. blah ... yatta ... yatta.



cparrish@sewanee.edu